/*
 * Arm SCP/MCP Software
 * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef SCP_MMAP_H
#define SCP_MMAP_H

#include "tc4_atu.h"

/* SCP TCM size */
#define SCP_ITCM_SIZE (256 * 1024)
#define SCP_DTCM_SIZE (256 * 1024)

/* SCP TCM base addresses */
#define SCP_ITCM_NS_BASE 0x00000000
#define SCP_ITCM_S_BASE  0x10000000
#define SCP_DTCM_NS_BASE 0x20000000
#define SCP_DTCM_S_BASE  0x30000000

/* SCP Boot and Runtime base addresses */
#define SCP_BOOT_BASE    SCP_ITCM_S_BASE
#define SCP_RUNTIME_BASE SCP_DTCM_NS_BASE

/* SCP Boot and Runtime maximum sizes */
#define SCP_BOOT_SIZE    SCP_ITCM_SIZE
#define SCP_RUNTIME_SIZE SCP_DTCM_SIZE

/* SCP trusted and non-trusted RAM base address */
#define SCP_TRUSTED_RAM_BASE    (SCP_ATU_LOG_ADDR_SHARED_SRAM)
#define SCP_NONTRUSTED_RAM_BASE (SCP_ATU_LOG_ADDR_SHARED_NSRAM)

/* Secure Shared memory between AP and SCP */
#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE)
#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB)

/* Non-secure Shared memory between AP and SCP */
#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE)
#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB)

#define SCP_PERIPHERAL_BASE UINT32_C(0x44000000)
#define SCP_PIK_SYSTEM_BASE UINT32_C(0x57000000)

/* System Control Register Block Base Address */
#define SCP_SYSTEM_CONTROL_BASE UINT32_C(0x58021000)

/* Base address of the SCP ATU */
#define SCP_ATU_BASE (0x50150000)

#define SCP_UART_BOARD_BASE (0x4A040000)

#define SCP_PIK_SCP_BASE (SCP_PIK_SYSTEM_BASE + 0x200000)

#define SCP_GTCLK_CNTCONTROL_BASE (SCP_ATU_LOG_ADDR_GTCLK)
#define SCP_GTCLK_CNTCTL_BASE     (SCP_ATU_LOG_ADDR_GTCLK_AP)
#define SCP_GTCLK_CNTBASE0_BASE   (SCP_GTCLK_CNTCTL_BASE + 0x10000)

#define SCP_PIK_CLUSTER_BASE (SCP_PIK_SYSTEM_BASE + 0x40000)
#define SCP_PIK_DPU_BASE     (SCP_PIK_SYSTEM_BASE + 0x7C0000)
#define SCP_PIK_GPU_BASE     (SCP_PIK_SYSTEM_BASE + 0x80000)

#define SCP_UTILITY_BUS_BASE (SCP_ATU_LOG_ADDR_CLUSTER_UTIL)
#define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000)
#define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + ((n)*0x100000))
#define SCP_PPU_SYS0_BASE    0x5B800000
#define SCP_PPU_SYS1_BASE    0x5B810000
#define SCP_PPU_CME_BASE(n)  (SCP_PPU_CORE_BASE((n) + 8))

/* AMEVCNTR1 address offset from AMU base address */
#define SCP_AMU_AMEVCNTR1_OFFSET 0x100

#define SCP_MPMM_BASE               (SCP_UTILITY_BUS_BASE + 0xB0000)
#define SCP_MPMM_CORE_BASE(CPU_IDX) (SCP_MPMM_BASE + ((CPU_IDX)*0x100000))
#define SCP_AMU_BASE                (SCP_UTILITY_BUS_BASE + 0x90000)
#define SCP_AMU_CORE_BASE(CPU_IDX)  (SCP_AMU_BASE + ((CPU_IDX)*0x100000))
#define SCP_AMU_AMEVCNTR0X(CPU_IDX) (SCP_AMU_CORE_BASE(CPU_IDX) + 0x0)
#define SCP_AMU_AMEVCNTR1X(CPU_IDX) \
    (SCP_AMU_CORE_BASE(CPU_IDX) + SCP_AMU_AMEVCNTR1_OFFSET)

#define SCP_MHU_SCP_AP_RCV_NS UINT32_C(0x401f0000)
#define SCP_MHU_SCP_AP_SND_NS UINT32_C(0x401e0000)
#define SCP_MHU_SCP_AP_RCV_S  UINT32_C(0x40170000)
#define SCP_MHU_SCP_AP_SND_S  UINT32_C(0x40160000)

#if defined(PLAT_FVP)
#    define SCP_MHU_SCP_RSS_RCV_S_CLUS0 0x5a010000
#    define SCP_MHU_SCP_RSS_SND_S_CLUS0 0x5a000000

#    define SCP_MHU_SCP_RSS_NUM_DBCH (4)
#endif

#define SCP_PLL_BASE         (SCP_ATU_LOG_ADDR_PLL)
#define SCP_PLL_SYSPLL       (SCP_PLL_BASE + 0x00000000)
#define SCP_PLL_GPU          (SCP_PLL_BASE + 0x00000008)
#define SCP_PLL_DISPLAY      (SCP_PLL_BASE + 0x00000014)
#define SCP_PLL_PIX0         (SCP_PLL_BASE + 0x00000018)
#define SCP_PLL_PIX1         (SCP_PLL_BASE + 0x0000001C)
#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020)

#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100)
#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)
#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C)

/* CCSM registers */
#define SCP_CCSM_BASE   (SCP_ATU_LOG_ADDR_CCSM)
#define SCP_CCSM_DSU    (SCP_CCSM_BASE + 0x000000)
#define SCP_CCSM_LIT    (SCP_CCSM_BASE + 0x010000)
#define SCP_CCSM_CME    (SCP_CCSM_BASE + 0x020000)
#define SCP_CCSM_MID    (SCP_CCSM_BASE + 0x030000)
#define SCP_CCSM_BIG    (SCP_CCSM_BASE + 0x040000)
#define SCP_CCSM_GPUTOP (SCP_CCSM_BASE + 0x100000)
#define SCP_CCSM_GPUSC  (SCP_CCSM_BASE + 0x110000)
#define SCP_CCSM_GPUNE  (SCP_CCSM_BASE + 0x120000)
#define SCP_CCSM_GPUCGP (SCP_CCSM_BASE + 0x130000)

/* AP Context Area */
#define SCP_AP_CONTEXT_BASE \
    (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \
     SCP_AP_CONTEXT_SIZE)
#define SCP_AP_CONTEXT_SIZE (64)

/* SDS Memory Region */
#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE)
#define SCP_SDS_MEM_SIZE (3520)

/* SCMI Secure Payload Areas */
#define SCP_SCMI_PAYLOAD_SIZE       (128)
#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE)
#define SCP_SCMI_PAYLOAD_S_P2A_BASE \
    (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)

/* SDS Memory Region of RSE - Reserved */
#define RSE_SDS_MEM_BASE (SCP_SCMI_PAYLOAD_S_P2A_BASE + SCP_SCMI_PAYLOAD_SIZE)
#define RSE_SDS_MEM_SIZE (64)

/* SCMI Non-Secure Payload Areas */

#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE)
#define SCP_SCMI_PAYLOAD_NS_P2A_BASE \
    (SCP_SCMI_PAYLOAD_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)

#define SCMI_FAST_CHANNEL_BASE \
    (SCP_SCMI_PAYLOAD_NS_P2A_BASE + (3 * SCP_SCMI_PAYLOAD_SIZE))

#endif /* SCP_MMAP_H */
